Challenge

Our client, a multinational corporation and semiconductor company that develops computer processors and related technologies, wanted to develop new data center accelerators using CDNA 3 architecture. This design, which combines multiple chiplets on a single interposer, addresses significant challenges in power, area, and timing optimization for high-performance computing (HPC) and generative AI workloads.

The project’s complexity required coordinating 200+ engineers across multiple geographical locations to develop 150+ functional blocks simultaneously. This global team structure demanded robust systems to maintain technical consistency while meeting ambitious deadlines driven by market opportunities.

Solution

In executing this substantial server chip design project, Quest Global delivered both technical expertise and project management:

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Took complete ownership of RTL design and integration, design verification, design for testing, physical design including tape-out and PDI functions support, and enhanced project flow and methodology

Managed an adept team of 200+ engineers during the project, with about 25 on the design team

Implemented a range of specialist tools, including Synopsys, Cadence, and Mentor, alongside company-specific internal tools and scripts

Results – At A Glance

Launched the industry's first integrated AI-HPC chipset ahead of competition by deploying our local-global model for maximum impact and efficiency

The client launched the industry’s first integrated AI-HPC chipset ahead of the competition, by deploying our local-global model for maximum impact and efficiency

Improved overall project performance in quality, cost, and delivery by introducing automation on methodologies

Enhanced the overall project performance in terms of quality, cost, and delivery, by introducing a range of automation on methodologies

Provided client support from multiple countries throughout the project duration

Delivered client support from multiple countries for the entire duration of the project

Accelerated ramp-up on new and complex architecture

Accelerated ramp-up on new and complex architecture